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T1: A RISC-V Vector processor implementation

T1: A RISC-V Vector processor implementation

6 comments

·February 3, 2025
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camel-cdr

Here is a list of open sourve RVV implementations: https://github.com/stars/camel-cdr/lists/rvv-implementations

They have varying progress and target performance.

explodingwaffle

TIL this github "list" feature. neat

Neywiny

Might be interesting to see this combined with vex. Also nice to see the recognition that memory bandwidth is an important consideration.

crest

Some of the old Cray machines only cached instructions and scalar data. Instead of a vector cache they used vector scratchpad registers and plenty of interleaved memory channels to keep up with the vector ALUs. That's one part of the design space you can't go RISC-V without yet an other vendor extension.

JoachimS

Would love to have seen some benchmarks.

hassleblad23

Very cool