Show HN: Strange Attractors
blog.shashanktomar.com
RSF forces in Sudan's civil war are preparing for mass genocide
economist.com
How I stopped worrying and started loving the Assembly
medium.com
Myths Programmers Believe about CPU Caches (2018)
software.rajivprab.com
S.A.R.C.A.S.M: Slightly Annoying Rubik's Cube Automatic Solving Machine
github.com
Futurelock: A subtle risk in async Rust
rfd.shared.oxide.computer
Leaker reveals which Pixels are vulnerable to Cellebrite phone hacking
arstechnica.com
'Killing the Dead' Review: Watch the Graveyard
wsj.com
Introducing architecture variants
discourse.ubuntu.com
A theoretical way to circumvent Android developer verification
enaix.github.io
The Impossible Optimization, and the Metaprogramming to Achieve It
verdagon.dev
Nisus Writer: Schrödinger's Word Processor
tidbits.com
Solving the NY Times "Pips" game with F#
github.com
Beyond Smoothed Analysis: Analyzing the Simplex Method by the Book
arxiv.org
Active listening: the Swiss Army Knife of communication
togetherlondon.com
Hacking India's largest automaker: Tata Motors
eaton-works.com
My Impressions of the MacBook Pro M4
michael.stapelberg.ch
How We Found 7 TiB of Memory Just Sitting Around
render.com
Use DuckDB-WASM to query TB of data in browser
lil.law.harvard.edu
Perfetto: Swiss army knife for Linux client tracing
lalitm.com
Viagrid – PCB template for rapid PCB prototyping with factory-made vias [video]
youtube.com
Kerkship St. Jozef, Antwerp – WWII German Concrete Tanker
thecretefleet.com
Since the CPU is doing cache coherency transparently, perhaps there should be some sort of way to promise that an application is well-behaved in order to access a lower-level non-transparent instruction set to manually manage the cache coherency from the application level. Or perhaps applications can never be trusted with that level of control over the hardware. The MESI model reminded me of Rust's ownership and borrowing. The pattern also appears in OpenGL vs Vulkan drivers, implicit sync vs explicit sync. Yet another example would be the cache management work involved in squeezing out maximum throughput CUDA on an enterprise GPU.