Berkeley Out-of-Order RISC-V Processor (Boom) (2020)

camel-cdr

RISC-V is still at the point where open-source implementations (in rtl) are faster than purchasable proprietary ones (in silicon).

XiangShan is currently the fastest open-source CPU implementation: https://github.com/OpenXiangShan/XiangShan

uarch slides: https://tutorial.xiangshan.cc/hpca25/slides/20250302-HPCA25-...

uarch slides with WIP features: https://tutorial.xiangshan.cc/micro25/slides/Microarchitectu...

huyage

If I want to do systems research that needs a simple and synthesizable RISC-V design, what are some good options? BOOM seems to be pretty complicated and I don't really need the out-of-order execution.

I also want to be able to run it on a cheap FPGA, something like Artix A7.

rwmj

Rocket-chip is widely used (https://github.com/chipsalliance/rocket-chip). It can fit on smaller FPGAs.

If you want something very tiny and completely understandable, and don't mind that it's 32 bit, then PicoRV32 (https://github.com/YosysHQ/picorv32).

daedalus-

Try neorv32: https://github.com/stnolting/neorv32

huyage

Thanks. Looks good! Are you aware of any 64-bit options?

phkahler

The latest version seems to be Sonic Boom:

https://github.com/riscv-boom/riscv-boom

But this project seems to have stagnated with one significant commit in the last year.

HN

Berkeley Out-of-Order RISC-V Processor (Boom) (2020)

Berkeley Out-of-Order RISC-V Processor (Boom) (2020)