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OpenSERDES – Open Hardware Serializer/Deserializer (SerDes) in Verilog

OpenSERDES – Open Hardware Serializer/Deserializer (SerDes) in Verilog

2 comments

·June 18, 2025
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jauntywundrkind

Really awesome to see. Any kind of PHY type thing is awesome to see.

It's an under-told tale that open CPU's are "easy" to make, but if you actually want to actually run that chip it's everything else that makes it inordinately hard.

Probably like 99.9% of devices with USB hosts all use the same 4-5 different design families of host controllers. A huge number of sound chips are Cadence/Tensilica's HiFi 4/5 chip. Dram controllers, PCIe blocks... There's so many modular blocks used in making chips, where a pre-qualified design that already has been validated on a variety of fabs is just how everyone does it.

This is a 5 year old, barely updated project. There's no clear data on what was achieved that I can see here. But just getting a start doing chip design that interfaces with the world beyond the chip is a huge huge step forward. Building, characterizing what we get, tweaking & trying over again is what it's gonna take to make open source chips emerge & be able to stand on their own.

peter_d_sherman

Related (book):

"High-Speed Serial I/O Made Simple: A Designers’ Guide, with FPGA Applications" (2005):

https://www.xilinx.com/publications/archives/books/serialio....