RISC-V in AI and HPC Part 1: Per Aspera Ad Astra?
7 comments
·June 10, 2025justin66
kragen
It did (01978 to 01989), and RISC-V hasn't changed nearly that much since 02014 despite the introduction of important extensions like V, but there's an even more obvious falsehood: the RISC-V instruction set was introduced in 02010, not 02014. https://riscv.org/blog/2024/05/14-years-of-risc-v-a-journey-...
This article has a lot of huge honesty problems, but maybe the worst one is how it focuses exclusively on US companies, who aren't the ones doing the work of making RISC-V real. Where are the mentions of AliBaba, T-Head, WCH, Seeed Studios, Tencent, Pine64, Espressif, Rockchip, and all the other Chinese brands that are such huge players in the RISC-V world? This is like reading a news article about computer networking in 01984 in France that focuses entirely on Minitel and Groupe Bull and doesn't bother to mention Tymnet, IBM, Ethernet, Xerox, or the internet. Did MIPS hire a PR agency to write it for them?
Shilov himself has written about some of Huawei's RISC-V development, so he really has no excuse: https://www.tomshardware.com/news/huaweis-hisilicon-develops... Doesn't that seem a bit more significant than anything related to MIPS?
And in https://merics.org/en/report/huawei-quietly-dominating-china...:
> For instruction set architecture, the software for executing chip production which represents another key supply chain chokepoint with high levels of market concentration, China’s government has chosen an open-source architecture that was pioneered in the United States: RISC-V. Top artificial intelligence and software companies like Alibaba and Tencent have been charged with furthering progress in using RISC-V.
And Huawei's HarmonyOS supports RISC-V: https://www.huaweicentral.com/runhe-software-launches-harmon...
nullc
Has RISC-V gained a cmov yet or is security critical code still left do branch-and-pray or use byzantine bitops?
kragen
I'm sure at least one proposed extension has a constant time conditional move, but I don't know of a ratified extension has one. But as T-Head demonstrated with the V extension, shipped silicon can implement non-ratified extensions, and as the fast interrupt handling in WCH's CH32V003 demonstrates, shipped silicon can extend the architecture in ways that haven't even been proposed as extensions. But I don't know of any shipped silicon with a constant time conditional move, either.
For most people, though, using "byzantine" bitops in their security-critical code is less important than being able to run it on a processor that doesn't implement IME or other presumable US backdoors. (Huawei backdoors, though?)
null
curtisszmania
[dead]
The first sentence contains an obvious falsehood:
Introduced in 2014, the RISC-V instruction set architecture has been evolving at a pace that Arm and x86 ISAs have never experienced.
In eleven years the PC world went from having the 8086 to having the 80486.