Mathematical Compact Models of Advanced Transistors [pdf]
31 comments
·March 29, 2025eternauta3k
gautamcgoel
Suppose I achieved a breakthrough in nonconvex optimization. How would I sell it? Who in the semiconductor industry should I approach?
bgnn
TSMC, Samsung, Globalfoundries
somethingsome
Do you have some dataset? And targets? Some starting code for the simulation or a software name?
Koncopd
Why didn't the PhDs specializing in this area figure this out themselves?
eternauta3k
These are physics/EE PhDs. They are not experts in nonlinear optimization. Some (those with more programming skills) experiment with fancier optimization algorithms (see links), but there is a long way to go.
https://ieeexplore.ieee.org/abstract/document/9796144
godelski
> These are physics/EE PhDs.
> They are not experts in nonlinear optimization.
No one that is an expert in nonlinear optimization has a PhD in... nonlinear optimizations. Typically their degree is going to be in Mathematics, Computer Science, Electrical Engineering, or Physics. The last 2 are commonly found in any strongly mathematical subfield.
This is kinda like saying a physicist can't program or is terrible. Maybe they can, maybe they can't. My senior undergrad CS students are worse programmers than most graduate physicists I've seen. One of the best programmers I know has a PhD in Mechanical Engineering and works at a national lab. I asked him how it ended up like that and he said to get his PhD work done he had to do a lot of low level stuff, related to what we were doing.
I do agree with your point fwiw, I just thought if we're going to nitpick we should nitpick ;)
noosphr
This is from 2018, anyone in the field know if it's still state of the art or a historic curiosity? I know that we've started using euv since then which seems like it would change things.
momoschili
This might be changing with the slowdown in node advancements, but I think it's unlikely you are going to get anything truly "state-of-the-art" in publication research. Academia has trailed industry in this kind of transistor level semiconductor physics for years now. The majority of the state-of-the-art models are closely held in your usual suspects (Intel, TSMC, etc), and are likely considered significant trade secrets.
adrian_b
The models themselves belong to the companies that make the software EDA tools for circuit simulation, i.e. Synopsys, Cadence, Siemens (ex Mentor).
While the models used in commercial EDA tools are based on those published by academic research, they may have various secret tweaks.
What belongs to the foundries, e.g. TSMC, Samsung, Intel, UMC, Global Foundries etc., or to the in-house semiconductor plants of certain companies, are the values of the model parameters, which are determined by fabricating and measuring a lot of test devices.
The foundries provide the model parameters to their customers included in the so-called Process Design Kits. For each semiconductor device fabrication process there is a PDK.
In order to design some custom integrated circuit, you need to obtain the PDK and install it in your simulation tools.
Unfortunately, the foundries with up-to-date fabrication processes keep secret their PDKs. Otherwise many people could attempt to design something like a CPU competitive with Intel, because unlike for fabrication, for design all you need is a computer and time.
Attempting to design a CPU using one of the obsolete PDKs that are available publicly, which are at the level used for CPUs like Pentium 4, more than 20 years ago, is futile, because the optimal design choices are very different for such ancient CMOS fabrication processes, in comparison with modern processes, so you would not learn more from that experience than when targeting an FPGA.
RicoElectrico
Isn't it that models themselves are public (like BSIM) but what you get in a PDK is a macromodel wrapping BSIM with another zillion of fudge factors, or at least binned by device size? That's what I understood by peeking into various PDK models.
eternauta3k
Aren't the fab models usually rough and binned? Which is why companies have modeling departments.
bgnn
nope. Fab models are extremely accurate for mature nodes (like anything down to 3nm now). They keep updating after qualification runs, but you see they converge within 1-2 years. Even failure modes and probabilities are modelled extremely accurately
This is if you run full electrical circuit simulation. For complex digital chips you can't do that due to insane compute requirements. There comes in modeling and yield estimation wizardry in. But if you want to simulate the hell out of a reasonably small circuit (< 100M nodes), you can do that extremely accurately.
wtallis
> I know that we've started using uev since then which seems like it would change things.
Are you asking about EUV lithography? That's a manufacturing technique, but this thesis is about modeling the physics of how a transistor operates, not the process of building the transistor.
sitkack
They are implying that due to smaller features, the transistors change and if these models still hold for those smaller transistors.
Classic hn well akshully.
momoschili
Well I think both commentators are valid- the effect of shrinking a transistor but keeping the same geometry is probably well captured by this model. Going from a "10 nm" DUV finFET to a "7 nm" EUV finFET, this model probably works quite well whether you're manufacturing using EUV or DUV.
I think the crux of the matter is the transition from 7 nm down to our modern nodes, where the major change was not only going from DUV to EUV, but perhaps more importantly the change from finFET to multi-gate or gate-all-around FET (GAAFET), where this model probably needs significant updates to be still valid.
westurner
State of the art in transistors?
- "Researchers get spiking neural behavior out of a pair of [CMOS] transistors" (2025) https://news.ycombinator.com/item?id=43503644
- Memristors
- Graphene-based transistors
EUV and nanolithography?
SOTA alternatives to EUV for nanolithography include NIL nanoimprint lithography (at 10-14nm at present fwiu), nanoassembly methods like atomic/molecular deposition and optical tweezers, and a new DUV solid-state laser light source at 193nm.
quantum_state
Wonder if there is an update on the arts … nice to have accurate model of a few transistors … however, with chips operating at GHz, physical layout and the interaction among the circuit elements may seem to be more challenging to take care of …
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ur-whale
It's indeed from 2018 and may therefore not be state of the art, but, it's really nice to read something like this: it cuts through all the marketing hype and pseudo-science-reporting articles written on cutting edge semis of the 21st century.
Getting an accurate idea of how things really work down at that level is very refreshing.
Also, it scratches an itch I've had for a long time, namely to understand how much quantum mechanics is really needed to accurately predict/model modern FETs.
eternauta3k
If you want to learn and have a physics/EE background, you might have better luck with a book like Tsividis (also available as a MOOC!)
https://www.amazon.de/-/en/Operation-Modeling-Mos-Transistor...
thechao
The first chapter reads like the scientific equivalent of "hold my beer". I don't pretend to understand it, in the slightest, right now, but I love the style!
By the way, fitting compact models is largely done by PhDs spending weeks tweaking parameters to get the simulation to match measurements. If you can find a method to automate this (which very roughly comes down to minimizing a non-convex function of ~100 parameters) you can make a lot of money.