Rust on the RP2350 (2024)

Easily making static executables is a huge boon too.

They should have filled it with more SRAM instead - 520KB is far too little.

Source for the RISC-V cores being essentially free (Luke Wren is the creator of the RISC-V core design used):

> The final die size would likely have been exactly the same with the Hazard3 removed, as std cell logic is compressible, and there is some rounding on the die dimensions due to constraints on the pad ring design.

https://nitter.space/wren6991/status/1821582405188350417

Funny thing is that it cost them more than you might think. It was the ability to switch to the riscv which made it (much) easier to glitch. See the "Hazardous threes" exploit [1]

[1] https://www.raspberrypi.com/news/security-through-transparen...

I wonder if they're using the same die for one or more microprocessor products that are RISC-V-only or ARM-only? They could be binning dies that fail testing on one or the other cores that way. Such a product might be getting sold under an entirely different brand name too.

SRAM is very area intensive. What you're asking for is very greedy. The RISC-V core they are using is absolutely tiny.

two things:

1) it needs a certain perimeter to allow all the pins to go from the silicon to the package, which mandates a certain sized square-ish die 2) only the cores are duplicated (and some switching thing is added)

so yes, there is enough space to just add another two cores without any worries, since they don't need more IO or pins or memory or anything.

> so they decided to add RISC-V as a sort of feature test and market test;

After some thought I understand the problem this setup tackles: Without dual architectures, there's a conundrum: how do you sell Risc-V if everyone is tooled for Arm?

So I get that offering both means they dont have to risk tapeout of a pure Risc-V die there's no immediate market for. The dual arch chip presents little to no risk while allowing the same chip to bootstrap a Risc-V tooling ecosystem. Once the end users have a mature Risc-V ecosystem the chip makers can begin to cut the Arm licensing strings they are entangled in.

> It's more common than you think.

You are describing co-processors or accelerators which fulfill a different role in the same system. It makes sense to have those. However, I was initially confused as to why a chip needs two architectures that fulfill the same role. That did not make sense at first glance from a technical standpoint but does from a business one.

If anything, they must have learned by now that they can simply drop the ARM cores and go full RISC-V.

As long as they make their core at least feature-equivalent by implementing FPU and the secure boot chain.