Using the most unhinged AVX-512 instruction to make fastest phrase search algo
48 comments
·January 23, 2025nemoniac
queuebert
Dumb question: does modern stack layout randomization affect the efficiency of recursion? On first glance I would be worried about cache misses.
iamnotagenius
Imo the most "unhinged" cpus for AVX-512 are early batches of Alder Lakes which is the only cpu family that has nearly full coverage of all existing avx-512 subsets.
Namidairo
It's a shame that Intel seemed to really not want people to use it, given they started disabling the ability to use it in future microcode, and fused it off in later parts.
Aurornis
> It's a shame that Intel seemed to really not want people to use it
AVX-512 was never part of the specification for those CPUs. It was never advertised as a feature or selling point. You had to disable the E cores to enable AVX-512, assuming your motherboard even supported it.
Alder Lake AVX-512 has reached mythical status, but I think the number of people angry about it is far higher than the number of people who ever could have taken advantage of it and benefitted from it. For general purpose workloads, having the E cores enabled (and therefore AVX-512 disabled) was faster. You had to have an extremely specific workload that didn't scale well with additional cores and also had hot loops that benefitted from AVX-512, which was not very common.
So you're right: They never wanted people to use it. It wasn't advertised and wasn't usable without sacrificing all of the E cores and doing a lot of manual configuration work. I suspect they didn't want people using it because they never validated it. AVX-512 mode increased the voltages, which would impact things like failure rate and warranty returns. They probably meant to turn it off but forgot in the first versions.
adrian_b
They had to disable AVX-512 only because Microsoft was too lazy to rewrite their thread scheduler to handle heterogeneous CPU cores.
The Intel-AMD x86-64 architecture is full of horrible things, starting with the System Management Mode added in 1990, which have been added by Intel only because every time Microsoft has refused to update Windows, expecting that the hardware vendors must do the work instead of Microsoft for enabling Windows to continue to work on newer hardware, even when that causes various disadvantages for the customers.
Moreover, even if Intel had not said that Alder Lake will support AVX-512, they also had not said that the P-cores of Alder Lake will not support AVX-512.
Therefore everybody had expected that Intel will continue to provide backward compatibility, as always before that, so the P-cores of Alder Lake will continue to support any instruction subset that had been supported by Rocket Lake and Tiger Lake and Ice Lake and Cannon Lake.
The failure to be compatible with their previous products has been a surprise for everybody.
Dylan16807
The reason you had to disable the E cores was... also an artificial barrier imposed by Intel. Enabling AVX-512 only looks like a problem when inside that false dichotomy. You can have both with a bit of scheduler awareness.
ack_complete
The problem with the validation argument is that the P-cores were advertising AVX-512 via CPUID with the E-cores disabled. If the AVX-512 support was not validated and meant to be used, it would not have been a good idea to set that CPUID bit, or even allow the instructions to be executed without faulting. It's strange that it launched with any AVX-512 support at all and there were rumors that the decision to drop AVX-512 support officially was made at the last minute.
As for the downsides of disabling the E-cores, there were Alder Lake SKUs that were P-core only and had no E-cores.
Not all workloads are widely parallelizable and AVX-512 has features that are also useful for highly serialized workloads such as decompression, even at narrower than 512-bit width. Part of the reason that AVX-512 has limited usage is that Intel has set back widespread adoption of AVX-512 by half a decade by dropping it again from their consumer SKUs, with AVX10/256 only to return starting in ~2026.
fuhsnn
Do they cover anything Sapphire Rapids Xeon's don't? I thought they share the same arch (Golden Cove).
suzumer
According to this [1] wikipedia article, the only feature Sapphire Rapids doesn't support is VP2INTERSECT.
[1]:https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
nextaccountic
It seems that there are faster alternatives to it
https://arxiv.org/abs/2112.06342
https://www.reddit.com/r/asm/comments/110pld0/fasterthannati...
iamnotagenius
Yes, you are right; I meant "consumer grade cpu".
adgjlsfhk1
What about Zen5?
nxobject
Spoiler if you don’t want to read through the (wonder but many) paragraphs of exposition: the instruction is `vp2intersectq k, zmm, zmm`.
bri3d
And, as noted in the article, that's an instruction which only works on two desktop CPU architectures (Tiger Lake and Zen 5), including one where it's arguably slower than not using it (Tiger Lake).
Meaning... this entire effort was for something that's faster on only a single kind of CPU (Zen 5).
This article is honestly one of the best I've read in a long time. It's esoteric and the result is 99.5% pointless objectively, but in reality it's incredibly useful and a wonderful guide to low-level x86 optimization end to end. The sections on cache alignment and uiCA + analysis notes are a perfect illustration of "how it's done."
tpm
Presumably Zen 5 cores will also get used in Threadripper and EPYC processors.
josephg
Yep. And the feature will probably be available on all AMD CPUs manufactured from here on.
It might be an esoteric feature today. But if it'll become an ubiquitous feature in a few years, its nice to learn about using it.
nine_k
What a post. It should have taken a week just to write it, never mind the amount of time it took to actually come up with all this stuff and overcome all the obstacles mentioned. What a dedication to improving the performance of phrase search.
rkagerer
Is the first example under The genius idea heading missing entry #3 below?
mary:
docs:
- 0:
posns: [0, 8]
- 1:
posns: [2]
- 3:
posns: [1]rstuart4133
I thought it's missing. However, he does introduce it with:
> The inverted index will look something like this:
He isn't wrong. It is indeed "something like".
jonstewart
The most unhinged AVX-512 instruction is GF2P8AFFINEQB.
camel-cdr
Here is Knuth introducing the MMIX instruction MXOR, which Intel later defined on vector registers under the name vgf2p8affineqb.
https://www.youtube.com/watch?v=r_pPF5npnio&t=3300 (55:00)
"This is an instruction that doesn't exist in any computer right now, so why should I put it in a machine, if it's supposed to be realistic? Well, it's because it's ahead of time."
mschuster91
MMIX? Now that's something I haven't heard in a long time...
bri3d
There's a pretty good list of weird off-label uses for the Galois Field instructions here: https://gist.github.com/animetosho/d3ca95da2131b5813e16b5bb1...
genewitch
I think I actually need that instruction and have a use case for it, and it does something with a matrix transpose so I might finally find a real world useful demonstration of a matrix operation I can cite to people who don't know what those mean.
mrandish
From my 1980s 8-bit CPU perspective, the instruction is unhinged based solely on the number of letters. Compared to LDA, STA, RTS, that's not an assembler mnemonic, it's a novel. :-)
pclmulqdq
"Load accumulator" (LDA)
vs
"Galois Field 2^8 affine transform on quad binary words" (GF2P8AFFINEQB)
The compression factor isn't quite the same on character count, but it's still abbreviated. :)
mananaysiempre
Incidentally, how is it a GF(2^8) affine transform? As best as I can tell, it’s a GF(2)^8 affine transform, i.e. an affine transform of vectors of bits with normal XOR addition and AND multiplication, and the polynomial defining GF(2^8) just does not enter anywhere. It does enter into GF2P8AFFINEINVQB, but I’m having difficulties finding a geometric description for that one at all.
inopinatus
Sometimes I read through the instrinsics guide just to play the game of spotting instructions defined primarily because certain cryptologic agencies asked for it.
pclmulqdq
What about GF2P8AFFINEINVQB?
LarsKrimi
It has a fixed polynomial, so not really that useful for anything but AES
The only case where I've had use of GF(2^8) inverses is in FEC algorithms (Forney's algorithm) and then you need some kind of weird polynomial. But all of those needs are rarely in the hot-path, and the FEC algo's are way outdated
pclmulqdq
I think the AFFINE and AFFINEINV instructions are specifically for FEC and maybe compression algorithms. I also think they smell like something requested by one of the big customers of Intel (e.g. the government).
jonstewart
potato, potato, tomato, tomato
Fascinating blog post. Having said that, it may seem like nitpicking but I have to take issue with the point about recursion, which is often far too easily blamed for inefficiency.
The blog post mentions it as one of the reasons for the inefficiency of the conventional algorithm.
A glance at the algorithm shows that the recursion in question is a tail call. This means that any overhead can be readily eliminated using a technique known for nearly fifty years already.
Steele, Guy Lewis (1977). "Debunking the "expensive procedure call" myth or, procedure call implementations considered harmful or, LAMBDA: The Ultimate GOTO". Proceedings of the 1977 annual conference on - ACM '77.