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Isle FPGA Computer: creating a simple, open, modern computer

jecel

Though DVI/HDMI monitors are supposed to handle 640x480, over half of the ones I have tested don't display anything. Every single one of them worked just fine at 1280x768, however, so I am changing my projects to use that.

WillFlux

I'm surprised by this. 1280x768 is an unusual resolution, what display timings are you using?

I've found 1024x768 and 1280x720 are both well supported. I tend to use these display timings: https://projectf.io/posts/video-timings-vga-720p-1080p/

mercnz

did you try at 60hz? i've found a lot of monitors don't like 70mhz 720x400.. which is what bios often boots to on older computers. i'm not sure if they're running 640x480 at high refresh rate too.

Western0

I need 10 bits per word. (mebye 2 for error correct)

WillFlux

Hello, I'm the author of the Project F blog. I'd be happy to field any questions you have.

OrvalWintermute

64bit RISC5 is cheap & has significant advantages around address space, computational efficiency, and suitability for high-performance applications while being more future-proof for complex systems.

It is cheap also, with the F133*, priced at approximately $1.00 to $1.50 per unit in bulk

If looking more for US stuff (fabbed in South Korea), PIC64GX1000 can be as little as $21 but much more capable.

mk_stjames

I think the point of this project hinges on putting the CPU arch down to the FPGA - buying prebaked silicon in the form of an off the shelf risc-v CPU defeats most of the purpose.

The purpose being everything can be built from the bottom up and at no point is any part of it out of the scope of inspection. You never actually know what is spun into a that PIC64GX1000 because you didn't place and route and oversee the fab yourself.

Just because an ISA is 'open' like risc-v does not mean you know how it was implemented on-die.

Having all the verilog and using Yosys+nextpnr to generate the layout for the FPGA is (about) as close to knowing the provenance of the whole stack as you can ever get.

jecel

Please note that RISC-V and RISC5 are different projects:

https://riscv.org

https://riskfive.com

Despite the name of the second site, the actual processor is called RISC5 (see the menu on the left) and is part of the Oberon project by Niklaus Wirth.