Zen 5's AVX-512 Frequency Behavior
11 comments
·March 1, 2025Remnant44
eqvinox
Reading the section under "Load Another FP Pipe?" I'm coming away with the impression that it's not the LSU but rather total overall load that causes trouble. While that section is focused on transition time, the end steady state is also slower…
tanelpoder
I haven’t read the article yet, but back when I tried to get to over 100 GB/s IO rate from a bunch of SSDs on Zen4 (just fio direct IO workload without doing anything with the data), I ended up disabling Core Boost states (or maybe something else in BIOS too), to give more thermal allowance for the IO hub on the chip. As RAM load/store traffic goes through the IO hub too, maybe that’s it?
eqvinox
I don't think these things are related, this is talking about the LSU right inside the core. I'd also expect oscillations if there were a thermal problem like you're describing, i.e. core clocks up when IO hub delivers data, IO hub stalls, causes core to stall as well, IO hub can run again delivering data, repeat from beginning.
(Then again, boost clocks are an intentional oscillation anyway…)
kristianp
I find it irritating that they are comparing clock scaling to the venerable Skylake-X. Surely Sapphire Rapids has been out for almost 2 years by now.
fuhsnn
I think it's mostly the lack of comparable research other than the Skylake-X one by Travis Downs. I too would like to see how Zen 4 behaves in the situation with its double-pumping.
eqvinox
Seemed appropriate to me as comparing the "first core to use full-width AVX-512 datapaths"; my interpretation is that AMD threw more R&D into this than Intel before shipping it to customers…
(It's also not really a comparative article at all? Skylake-X is mostly just introduction…)
adrian_b
True, but who would bother to pay a lot of money for a CPU that is known to be inferior to alternatives, only to be able to test the details of its performance.
Szpadel
I'm curious how changing some OC parameters would affect those results if that it caused by voltage drop, how load line calibration affects it? is that's power constraint then how PBO would affect it?
It's interesting that Zen5's FPUs running in full 512bit wide mode doesn't actually seem to cause any trouble, but that lighting up the load store units does. I don't know enough about hardware-level design to know if this would be "expected".
The fully investigation in this article is really interesting, but the TL;DR is: Light up enough of the core, and frequencies will have to drop to maintain power envelope. The transition period is done very smartly, but it still exists - but as opposed to the old intel avx512 cores that got endless (deserved?) bad press for their transition behavior, this is more or less seamless.